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But the Kelvin connections!!?!!?!!
This is exactly it
Wasn't being used for current sensing though
@@Zachariah-Peterson hm, interesting and strange.
@@Zachariah-Petersonnow i see capasitor and resistor connected. Okey, sorry
@@SteepFreeman No worries, that's why i thought it necessary to say something, normally a current sense connection goes straight back to the regulator and into an amplifier, there would not be an RC circuit there.
Hmm yes, I understood some of those words.
😂
How'd you catch the C7 disconnect? Snap grids are your friend 😆
I noticed one of the pads in the layout did not have any net assigned to it, and everything was already synced between schematics and PCB. So I cross-probed and checked the connection.
Nice to hear from you after about 12 years :) Wishing you luck.
Thx, very interesting. Would love to talk to Greg for a day 😃!
I agree on the copper fills. Sometimes, its just hard to break the old habits practiced by seasoned pcb designers whenever we highlight on the concerns of emissions
I am interested in PCB design course basic to advanced training avelbel for you
Is there a beginner's programming tutorial for the GA144 ? That sounds like an awesome chip !
Btw, doing the routing of hi-speed-signals (including I/Os with considerable short rise/fall times) early and placing the return vias at the same time when they swith layers can reduce later problems/overhead-work to add the return vias.
Great video
Thanks so much!
Hi, Great video. Question about the the stackup. Why not PWR plane on layer 3? As you mention in the video the tight coupling between a PWR and GND layer is important at higher frequencies and in this way it would be closer to the top signal layer where the FPGA is.
PCB design is engineering and art in one package. Not everyone can do that.
Very true
I hate this
These guys change their tools every day. You cannot focus on your design anymore. You are constantly focused on learning where things are and by the time you figure it out they change it again. So frustrated
These guys change their tools every day. You cannot focus on your design anymore. You are constantly focused on learning where things are and by the time you figure it out they change it again. So frustrated
Thanks for sharing this info ! Are these the same capacitors can be used as a RC Snubber ? I dont see the ESR anywhere in the datasheet.
I dont think this video considers the ST part shown there actually has a large ground area and power area in the middle. So really 10 layers isnt needed.
Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/
Hello Zach Thank you for quickly review it is helpful to me. For the current limit ciruit, the buffer and comparator will be active to shutdown the mosfet separate with MCU. This circuit working but have a little problems for time respond. About the layout USB line. I must use 2 layer board for cost saving reason. I have use the impedance control function of Altium to keep impedance of USB differential pair at 90 Ohm +-10%. It is also good working and cost cheaper than 4 layer board. Thank you again for your time. Best regards, Duc.Chu
Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/
Tune in to the FULL Interview (releasing 5/14/24): kzread.info/dash/bejne/nm2hpKinnsjYZZs.html
I don't see why decreasing the self inductance of a trace will increase it's immunity to xtalk, I thought only the mutual inductance matters for inductive xtalk
This video provides valuable educational content, and I truly appreciate it. Thank you for sharing such helpful information. I have a question regarding impedance matching: I need to match an input impedance of approximately 1 kilohm to an output impedance of 50 ohms. Do you believe that I can achieve this using the Excel file you mentioned? Your assistance would be greatly appreciated. Thank you.
Are the PCB cut outs even needed since that looks like a 5-6mm gap so creapage and clearance is 5-6mm but also since it is under chips there are some patch unaffected so the minimal creapage is still the same as without the milled parts ?
He also did not pay attention to the fact that the contours of the board cutouts should be rounded to make it easier for the cutter to pass through
I actually mentioned that in the raw film but it did not fit into our 1 minute time allotment
@@Zachariah-Peterson Thanks for the answer and for making great content
Thank you for the anti-creepage slot. I would have taken it all the way through the capacitor and optocoupler (again, standard/best practices). Regarding the silkscreen, as a final step you can modify the footprints for individual components to meet your DRC requirements. In these cases, just breaking a few lines would do.
Ain't nobody got time to modify a few silkscreen lines just for a creepage slot!
@@Zachariah-Peterson The board is manufacturable, but it fails a basic DRC? You put all that effort into getting to the one yard line. Push through for the touchdown!
can you tell us about how much $ were those transformers? asking mostly like how much was the core+former and how much was the coiling process since i never ordered stuff like this before.
HI Zach, I often see pcb layout recommendation saying that output cap of a psu should be placed close the output pin of the PSU. But wouldn't it be better to place an outpur cap closer to the ic's sinking power from it, to bypass series parasitic inductance?
I would have placed U8 above or underneath T1 (on the same bottom layer to reduce the length of the HV trace. The cutout in the middle, as you pointed out it's purely cosmetic. However, I would have placed a cutout around pin 8, to prevent whiskers going to the neighboring pins.
Around 9:00, is that slot in the whole board, or just in the copper layer? (It looks sort of like a slot in the whole board but _not_ the copper layer, but that doesn't make sense...) Also, if the frequencies are low enough to justify separation like that, should the connection really be close to the BVDD/BGND like that, or would it be better to do it near the top/bottom of the package?
😊😊 😊⁰,9,
I'm in the middle of a PoE flyback design and this video comes in very useful, thanks !
Was I misreading the drill file around 17:11? It looked like there were several hole types that differed only in size, but the difference was less than the tolerance. Is the cost of drill changes essentially nothing now? Or are manufacturers expected to optimize this on their own? Or was this just something not yet optimized? (And if so, how did they get different sizes in the first place?)
For testing the transformer you should also consider measuring the primary leakage inductance. Short out the secondary coil and measure the primary at the intended operating freq. Having too much could kill the switch if the RCD clamp isn't tuned well. There is sooo much more that could be tested here. Hope to see a video on that soon.
We did this in another video where we looked at the design of the custom transformer and the clamp circuit. It came out to about 5%, which was actually less than I expected given it's an off-the-shelf core and bobbin.
OnTrack logo covering information on the video all the time, annoying! Please pay attention on where you add your publicity.
Do I understand correctly that shield of usb-connector should connect to gnd directly?
Yes.
This is a very important feature for me as an Altium user. I have been using this since it was first released with altium and the product has grown from unusable to nearly fully featured in less than a year. I look forward to where this product goes in the future. The biggest feature missing is scaled harness drawings. A very basic feature of harnessing software is the ability to set a bundle length and print a harness where the actual bundle length matches what you set in the harness drawing software.
If you shouldn't use a ferrite, ever... why do they exist? It could be a video: "why and how to use a ferrite?"
@Zachariah: Can you create a review on ESD/EFT/Surge Protection of small PCBs with no Frame/Chassis/Earth ground connection - with only power return or heat dissipation available for dumping the EOS?
It would be very interesting
🔹 Connect with Zach: Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/
🔹 Connect with Zach: Want your design reviewed by Zach? Reach out to him on LinkedIn with your design and production files for a chance to be featured on our channel: www.linkedin.com/in/zachariah-peterson/
I enjoy your reviews, how I can send you one of my designs?
Reach out to him on LinkedIn with your design and production files: www.linkedin.com/in/zachariah-peterson/
"Best time to use a ferrite is never" Isn't that a bit far fetched? Surely it has to help sometimes
I bet it has its uses. Feels like the argument about split ground planes. Some say never to do it but I have heard from some that it helps in low frequency applications. Is that true or not? Idk tbh I don't have enough experience.
@@alexanderquilty5705 I think the point is that it is so hard to use them correctly that never using them is a better choice
@@alexanderquilty5705 Ferrites work fine if the load has a very low current demand - peak current is almost irrelevant because there should be local bypass after the ferrite. This means unless your whole system is low current, each ferrite should really only be used to provide filtering for a specific low-power chip usually. For planes, it also has everything to do with how much current you're dealing with and the frequency. At audio frequency, it's very common to see split, bus, and star grounding. Once you get to 100kHz and above there's almost never a reason to do anything but a solid ground plane. Very often application notes will wrongly suggest bad grounding or decoupling schemes. Power planes are also usually pointless and only create more problems than they solve until you get into 10+ amp currents. At high frequencies copper pours often create more problems than they solve too. In the end just remember your return currents will go somewhere, whether you're aware of where they end up or not, and anything without a good low impedance path is going to propagate throughout the cavity inside the PCB instead or in anything else nearby to find its way back.
@@alexanderquilty5705 In some low frequency systems involving precision measurement it can be useful, but if you isolate a ground island for a low SNR DC measurement with a ferrite you better hope you don't get any high frequency displacement current into that ground region, it will radiate strongly.
The ferrite to GND is unnecessary as it just impedes the return current. Also the capacitor helps to create a LC circuit that will resonate and paradoxicly add more noise to the system as the ferrite may be a lossy inductor but not a perfect one. Just adding the capacitor (I would do) or ferrite, would be good enough. Shield I would put on a different reference frame, not trough a capacitor to ground.
Agree about the ferrite, I would just ditch it entirely and use caps. About the shield, it's always a challenge when the design does not have a dedicated frame/chassis ground, such as a guard ring that connects back to the power input.
Should the isolated grounds be connected with a capacitor ?
It is common to bridge these with a capacitor to allow high frequency currents to pass through the system to the input side rather than radiating from the board. Use a low-leakage capacitor with a voltage rating that exceeds the galvanic isolation requirement. The value of the capacitor is less important, mostly it just needs to be larger capacitance than the parasitic capacitance of the isolation barrier.
@@Zachariah-Peterson for if my isolation is 3kV then the cap needs to be rated at 3kv or more, right? does it need to be class Y or can it be any type? Can it even be a PCB layer caps with the core as dielectric/insolation? i can get a few pF from that
@@sanjikaneki6226 You are correct in your example it would be 3 kV or higher. Typical values for the capacitance are a few nF. It is preferred to use class Y because this will fail to an open circuit if there is an electrical fault in the ground planes. If it were class X, then an electrical fault could cause the capacitor to fail as a short circuit and this would create a safety risk to the user of the device.
Best combo of people ever :D!
I just went back into using Linkedin after not using it for a while and I can't figure it out at all, no idea what's going on, the layout is confusing, too many things going on on the page. Another "update" that breaks things.
If you enjoyed this clip, be sure to tune in to the full conversation: kzread.info/dash/bejne/lKmlss-sf7G-YbQ.html
Sir thank you so much for teaching quarter wave transfor. from Turkiye. Best