Alphawave is a team of technology industry veterans and engineers with a nearly 20 year history of building successful Silicon/IP teams. Founded in 2017, Alphawave has already seen strong success and impact in delivering proven Silicon in leading 7nm and 5nm processes. Profitable since day one, Alphawave is investing heavily in our existing and future products. This has already resulted in Alphawave building one of the most technologically exciting and fastest growing businesses in the history of semiconductors.
Connecting the next generation of devices with our 1-112Gbps PAM4/NRZ unique, DSP based, multi-standard connectivity SerDes IP solutions leverage years of experience and R&D to build the most power efficient, high performance solution available on the market to enable devices of the future.
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Can you list some references to support the PSIJ, and RJ equations you quoted? Thanks for sharing
Excellent thanks 🙏👍👌💯
excellent content
Hi, that's a great video. I have a question about the COM margin in min 19:19. Are you using for that metric the Rx equalizer as per 224gpbs standard? I think if the Rx eq is getting more powerful, we can improve that number. However, we also need to look at the power, it's like a trade off at the final of the day. I know it's hard, but this might allow to user higher level modulation in next generations. Thanks!
Great and informative video. Now, 2 years after the video was published, was the CPO technology adapted for the 50T/100T switches?
bin sehr enttäuscht von Alphawave immer groß getönt KI und Zukunft und Wachstum und jetzt alles gesenkt tolle Wachstumsfirma...
Better and more informative than most 1 hour lectures :) Thx - nicely done.
no sound in this video?
Great learning experience for me ❤❤❤
How exactly do Alphawaves products differ from those of the competition? What makes alphawave better than a Broadcom, Marvell or Credo?
So what’s that all mean to a layman
Tony is God
You guys should give a glossary for the dozens of acronyms the presenter uses. It is essentially gibberish to the layman otherwise.
Data in/out in page 10 are wrong.
Thanks Tony! Very good summary!
Very nice content
@3m38s wrong statement. The onset of the skin effect REDUCES the inductance - not increases it. As the current density shifts to the conductor surface, the internal inductance component decreases, whereas the external inductance remains unchanged. The overall inductance, which is the sum of the two components, decreases by as much as 40% for typical traces on a PCB.
Love this series. Makes it easier to understand high speed stuff and how to use them from perspective of a digital engineer
Very helpful, Thank you! Where can we find the slides?
So did you float the company in UK to avoid the USA trade embargo on trading with China?
Nowt wrong with that is there?
I watched this
Thanks for share! This tech video is very useful and good for SerDes studier, can i share it on other video websites?
Very interesting, thanks!
Big cool
nice
Very helpful Thank you!
Thank you for sharing this video on PAM4. @5:12, it is mentioned a future 2-min tech talk on overcoming the 9dB SNR penalty will be given. Can you please make a video on this or at least share the relevant information on your website if possible?
DSP architecture used to have a power problem, but as the process keeps shrinking, the power is almost compatible in 7nm and DSP has a performance/process insensitive benefits.
very helpfull
Thanks this was really informative.. What kind of performance we expect from ADC is it like 5-6 bit flash or more complicated pipelined kind of architecture. Does ADC conversion delay hurts? What is the typical speed of DSP, It seems like this will also be really fast and closing the timing would be a challenge If there is a good reference I would love to go through that. Thanks a lot!
Hi, For the ADC resolution, you need to do a system-level evaluation where depending on factors such as the channel and how complex is the equalization that you want to do in DSP domain you can get the estimate of the minimum number of ADC bits required to maintain a certain bit error rate target. But in general, what I have seen is 5-6bits ENOB time-interleaved ADC. Each of the sub-ADCs are "usually" implemented as SAR. Regarding the DSP speed, I have seen values of 750MHz, even 1GHz. In my understanding, the definition of that speed is done based on the technology node that you use (As far as I can see, nowadays the trend is 7n (even 5n) for state-of-the-art implementations). I also think that you also need to consider factors such as power consumption to define the clocking speed of the DSP logic. References for these topics I would recommend IEEE publications. the journal of solid states circuits is possibly the best journal. There is also good material in conferences such as the International solid states circuit Conference (ISSCC) or CICC. Also, I need to mention that some professors have very useful material, such as professor Sam Palermo from Texas A&M. people(dot)engr(dot)tamu(dot)edu/spalermo/ecen720(dot)html
@@user1561 Very informative...
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