Robert Feranec/Fedevel had a video about what to connect shield to. The "simple answer" was "you connect it to the chassis" since it is an extension of the shield in the cable, which is not a signal ground. I forget what you're supposed to do when you don't have a chassis, but I'm sure the video will cover it The EEPROM for the FTDI chip will store the VID:PID pair, product name, serial, configuration, etc. You can program it with ftprog which is a free tool from FTDI. Given the EEPROM will be blank from the factory (unless you program it before soldering it to the board), the FTDI will come up with a VID:PID pair of ffff:ffff, but ftprog will be able to find it and then you can write some more sane values in to the EEPROM. 10 layers seems insane. You should be able to do it on 8. See Robert Feranecs video series about the Mt Olympus server motherboard which, fair to say, has many high speed interfaces, and is routed on 8 layers.

For JTAG - As I understand, for Zynqs it's recommended to use Digilent HS3 programmer as it provides also a Zynq reset line which is used during debugging. This is the programmer I was using before Xilinx published a tool which allows programming FT chips on custom boards, it uses Xilinx standard 2x7 connector with 2 mm pitch (which is rather annoying).

For FT2232 - it requires EEPROM (not flash), and it will be programmed over USB itself, so you don't need to worry about pre-programming anything before assembling. I typically connect USB shell to a system ground via 1M resistor and a high-voltage (200 V or higher) 1nF capacitor. The idea is to allow potentials on both sides to eventually equal, while limiting inrush current (hence high resistance), while shorting any high-frequency signals (to them the cap is going to look like a short).

If you want access to the widest possible capacity range for QSPI flash, you will have to go with BGA-24 package with 1 mm ball pitch - there are up to 2Gbit devices out there! This is the package of choice for me for that exact reason.

I recommend replacing full size SD card connector with microSD, which is much smaller, and most modern cards are actually sold as a microSD + full size adapter anyway.

DDR3 also requires termination for address and control signals (Address lines, BA0-BA2, CS, WE, RAS, CAS, CKE), and a 100 Ohm parallel termination resistor for clock line (connected between CKP and CKN, physically placed "after" all memory connections).

@monkev1199

Ай бұрын

The design in the video with two ram chips would probably need to be routed as fly-by and yes that would apply. Although I have also heard the termination is redundant if you have a point to point system (a single dram chip for example)

@asmi06

Ай бұрын

@@monkev1199 That is correct on both counts (though the latter with some caveats).

@monkev1199

Ай бұрын

For the latter I'm guessing it's based on length of traces?

@asmi06

Ай бұрын

@@monkev1199 That, and also a frequency (the higher the frequency, the shorter the traces have to be to be able to get away without termination). Ultimate judge here must be a simulation and/or experimentation.

@monkev1199

Ай бұрын

​​@@asmi06thanks for the info. I guess I'll be conservative and add the termination resistors on my own design (ECP5 SOM with DDR3)

Your power indicators are not the best design. I would recommend to cue them off "power good" signals of respective DC-DC converter instead of power rail (as right now your indicators indicate presence of "some" voltage, not necessarily the right one), also replace BJT transistors with MOSFETs as you don't want to waste power by running big currents through the base junction (unlike BJTs, MOSFET do not conduct current through gate terminal as it's electrically isolated from other terminals).

@rehsd

Ай бұрын

Great catch. Ya', that design wasn't great, and going off power good is much better. I will also swap out BJTs with MOSFETs. Thanks!!