Yield is a much bigger issue when it comes to panel-level packages, which may contain up to 24 RDL layers. Just finding the defects is a massive challenge, let alone understanding how they will impact the entire device. Many of these advanced packages are being used in data centers for generative AI, and killer defects caused by bridges and opens can cause serious problems. What happens, for instance, if you cannot test every layer? Keith Best, director of product marketing, lithography, at Onto Innovation, talks with Semiconductor Engineering about compounding yield issues, what is considered acceptable yield and cost, and how to track all of this through multiple steps and processes