One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at Arteris, talks with Semiconductor Engineering about defining which blocks need to talk to other blocks, building cache coherency into a design, and the different interfaces that need to be considered in a complex system.