You mention that part of the problem is reduced impedance from the traces getting closer together. Does that mean it would help to put the vias to the outside, eating into the separation from other traces, rather than the separation between them? _0 instead of -0 ?

@Zachariah-Peterson

Жыл бұрын

I would say yes this is appropriate and it is usually the way I would do this on something very fast like CSI. I'll show an example in our next Q&A vid

I'm going to throw this question out here for anyone with the right knowledge to help me. I'm working on a SiCFET motor inverter where the SiCFETs have a rise time of 25 to 30ns and a fall time of 10 to 15ns with a carrier frequency of 20kHz and running the motor in PWM mode from 3% to 97% duty cycle (3 phase). We have additional functionality that is used outside of the normal PWM run mode that takes advantage of the quick rise and fall times. Given the SiCFETS are a Kelvin source configuration, should I be treating the gate and kelvin source as a differential pair? Another engineer has been leading the design on this project, but we have had just one failure after another. At $10k a pop, these failures have added up to a huge chunk of our budget. I'm looking into the circuit and PCB design on my own time, trying to find as many points of possible issue that I can. He has been treating the gate and kelvin source traces like normal, low speed, MOSFET traces

You told how to use tNice tutorials program like I was 6 and it was perfect

Dear Zach, thanks for your brilliant video! You've mentioned about an article in the description of the video about using teardrops as tapers. Maybe you forgot to attach this. Could you please share it?

@Zachariah-Peterson

Жыл бұрын

It is in the description, the title is "Should You Place Teardrops on Differential Pairs?"

@pavelkobrisev2574

Жыл бұрын

@@Zachariah-Peterson Yeah, exactly! Initially I was a bit confused and tried to search an arricle with a title that included word "tapers". I've already looked through it, very useful as usually! A curious thing that I've noticed, that it is not mandatory to make the lenght of the taper equal to quarter wavelength. I thought that this parameter shouldn't vary and the length lambda/4 is a strict criteria for impedance matching.

@Zachariah-Peterson

Жыл бұрын

@@pavelkobrisev2574 I'll do a video on the Klopfenstein taper because it's a good example where you don't use a quarter wavelength match, and you get broader bandwidth matching.

@pavelkobrisev2574

Жыл бұрын

@@Zachariah-Peterson Sounds like a Black Magic)) Thanks for your efforts! Looking forward to your next videos!

What if you move the vias far from each other so that you keep the same distance w between the 2 edge of the via's annular ring? I think in that case we not have a difference in the impedance as the distance didn't change.

@AMalas

Жыл бұрын

Then you'd have a possibly larger impedance discontinuity in the vias themselves

@Zachariah-Peterson

Жыл бұрын

This is a great question and you would need to maintain some ratio between the spacing and width to ensure you always have the correct odd-mode and differential impedance values. I went over this in our Q&A video, it should come out soon!

Hi sir can we route address command and ctrl signals on different layers with lenght match in ddr3 layout

@Zachariah-Peterson

7 ай бұрын

Yes you can route signals in this way, all that really matters is to ensure you have consistent impedance and total propagation time on both layers. As long as you satisfy these constraints then you can route the interface on different layers.

Is there a way to make round traces instead of right angle and 45 degrees? Or generally follow a curved route with an inflection point when connecting two parts that are not aligned with each other?

@CodyLynn100

Жыл бұрын

Yes, so long as the router you are using includes an option or setting to allow this.

@jimjjewett

Жыл бұрын

Gerber files allow arcs as well as lines. For generic curves instead of just portions of a circle, just splice together a whole bunch of short pieces. How easy this is in your higher level tool varies ... Support for arcs has been one of the quality-of-implementation issues that some skimped on for decades.

@Zachariah-Peterson

Жыл бұрын

While routing, hit the tab key to pause the tool, then go into the Properties panel, below the geometry options you will see some options to select right-angle, circular, etc.

hello sir, what do you mean by class 3?

@AMalas

Жыл бұрын

I believe this refers to IPC reliability standards

@Zachariah-Peterson

Жыл бұрын

Yes I am referring to an IPC reliability standard, which will place requirements on annular rings during manufacturing. As a designer, this means you need to include a minimum pad size on vias based on the manufacturer's capabilities. For Class 2, the safest requirement is minimum 8 mil larger than the via drill diameter, and for Class 3 it is 10 mil larger than the via drill diameter. It's best to apply this on all layers where a pad is present. Some manufacturers will request that you include teardrops whenever you are manufacturing to Class 3 compliance.

Your drawing is R

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music is not necessary

You want to be a professor, but you still use mils as a unit of measurement.

@Zachariah-Peterson

Жыл бұрын

I guess you don't realize that I was teaching at a university 10 years ago. Been there, done that. Mils are a standard unit that is used in this field. Thanks for watching.