Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product marketing for Synopsys’ EDA Group, talks with Semiconductor Engineering about why the human body or charged device models are no longer sufficient protection, why stacking chips in a package increases the risk of a catastrophic event, and how to identify potential design violations that can worsen the impact of ESD.