Such an in-depth explanation. You work is simply amazing!!

@BhargavaAnurag

3 жыл бұрын

Thank you! Cheers!

Simply fantastic... I got to get a refresher on set up the ground planes, adding vias and ground planes.

@BhargavaAnurag

4 жыл бұрын

Good know that it was helpful...!!

Just one word: Amazing! I would say, the most comprehensive tutorial on LNA design at a practical level. Very good material for both experienced and beginner RF/MW engineers. As you said at the beginning, all the theoretical background is applicable for all the different available technologies. Great job! I look forward to see more high quality videos in the future! Thanks!

@BhargavaAnurag

3 жыл бұрын

Glad it was helpful and appreciate your kind comment.

Simple, organized, well explained ! Thanks a lot sir.

@BhargavaAnurag

3 жыл бұрын

Thanks for your feedback...Keep watching...👍

Amazing detail video on LNA, Thanks!!!

@BhargavaAnurag

2 жыл бұрын

Glad it was helpful!

your videos are just perfect. I really appreciate your effort to make these extraordinary videos. you have no idea ho much I have been benefitted from your tutorials as a communication engineering student

@BhargavaAnurag

2 жыл бұрын

Glad you like them!

Have never seen such an elaborate and detailed explanation of the LNA design flow. Implemented it myself in ADS this weekend following the steps in this video. Worked perfectly fine. Thanks a lot for your tutorials. These are the tenets for a radio engineer, no doubt about that. Eagerly waiting for your PA design tutorial. Thanks a lot sir.

@BhargavaAnurag

4 жыл бұрын

Glad it was helpful!

really awesome, i have never seen such likes videos so far, thanks a lot, we are waiting for you with another amazing work as well

@BhargavaAnurag

2 жыл бұрын

Thank you so much 😀

Thank you so much sir, your tutorial was a great help to me to complete my LNA design for my internship. You are the best in your domain sir.

@BhargavaAnurag

3 жыл бұрын

Hi Amer, Thanks for sharing your feedback and good to know that video was of some help to you...👍

great channel, great videos. hope to see more videos on rf design and mmic

@BhargavaAnurag

3 жыл бұрын

Sure...👍

Thank you so much sir this is a great tutorial !!!

@BhargavaAnurag

7 ай бұрын

Thanks...👍

Hi Anurag, this is really a helpful video that let me have a full picture on how to design a LNA and the role of simulator involved. Thanks!

@BhargavaAnurag

Ай бұрын

👍

Outstanding Job. 👍

@BhargavaAnurag

3 жыл бұрын

Thank you! Cheers!

Great job, thank you sir

@BhargavaAnurag

3 жыл бұрын

You are welcome

awesome,thanks so much

@BhargavaAnurag

3 ай бұрын

glad you liked it..👍

Masterclass👏

@BhargavaAnurag

10 ай бұрын

👍

If you are an RF Engineer, then I recommend you to Subscribe to this channel. Its a vast treasure trove. Its a privilege to listen to Mr.Anurag.

@BhargavaAnurag

3 жыл бұрын

Hi Ramesh, Thanks for your kind words. Hope you would be able to share the link of my channel with your friends & colleagues and ask them to subscribe...👍

@rameshbabu2704

3 жыл бұрын

@@BhargavaAnurag sure, I will !!

Thank you sir, really useful tutorial

@BhargavaAnurag

3 жыл бұрын

Glad it was helpful!

Hi Anurag , thanks you share the knowledge , it's really helpful

@BhargavaAnurag

10 ай бұрын

Glad to hear that

Kindly post a detailed video on Mixer design as well active as well as passive mixer. It's really very informative tutorial many thanks for uploading this.

@BhargavaAnurag

Жыл бұрын

Sure, will try to create something on mixer design soon.....

Thank you so much sir ...This video is very helpful for my research aspect on LNA design... could you please make some more video on microwave oscillator and mixer design concept.....I am eagerly waiting to see your next video on those topics..

@BhargavaAnurag

3 жыл бұрын

Hi Saurabh, As per current plan, Oscillator and Mixer topics are not to be covered in very near future as there are many topics before we reach there. However, if I could help by any other means then I would be happy to do so...

@qasheef

Жыл бұрын

@@BhargavaAnurag Hello sir, your work is amazing. I am also looking for your in depth tutorial on mixer and oscillator design. It would be great if you can help us in this regard.

Great videos sir. You think you would ever do lower frequency design tutorials for amateur radio. Coaxial balun/transformers tutorials are hard to come by. Thanks again.

@BhargavaAnurag

3 жыл бұрын

Hi Justin, I haven't done those kinds of designs myself but if you have some good paper showing the technologies and some design approaches then I can try to create a tutorial around it...

Thanks for creating these tutorials. They are extremely helpful. Do you have one that covers the creation of a "look-alike" EM model that can be used in the co-simulation of an amplifier design? I know this is what you used in this tutorial, however, the details of creating the model were omitted.

@BhargavaAnurag

3 жыл бұрын

Thanks for the reminder Abraham, I didn't create any special emcosim video covering look-alike model in detail but surely will upload a video on that pretty soon.

first at all, it’s a great video. Excellent. Some good book or papers where explain how to get the high frequency model of a FET? A mean the intrinsic parameters of the transistor.

@BhargavaAnurag

4 жыл бұрын

Hi Jhon, I am glad to know that you liked the tutorial. I am not keeping in great touch with books these days but old is gold and Gonzalez kind of book should have it....

@jhonjvare09

4 жыл бұрын

@@BhargavaAnurag Hey Sr. Once again, thank you for sharing your knowledge with us. Something special to avoid the use of the DC bias network?

@BhargavaAnurag

4 жыл бұрын

I am not sure what you want to ask, DC Bias Network cannot be avoided as you need to feed DC for active transistors to work and also to isolate DC from RF. How you end up doing this network designs depends on your design frequency and you either use Choke method on lower frequency ranges and use lamda/4 approach for high frequencies for RF board applications...

Great video and direct design approach explaining fundamentals. I am new to ADS layout tips. Could you please redirect me to the video where you describe gnd plane creation and array of vias ? Thanks in advance

@BhargavaAnurag

3 жыл бұрын

Hi Anand, You can watch Tutorial 41 and 42 under Learn ADS in 5mins playlist and you will get answer to your query.

Very good, but if you included actual substrate/package dependent lumped competent models, it would give even more accurate results, models like the ones available from Modelithics.

@BhargavaAnurag

3 жыл бұрын

Hi Mohd, In some cases what you say will be important however one need to realize that those models aren't free and not many designers may want to buy them hence I need to show what can be done with bare necessities. In the LNA case I shown in the video, it won't matter much if you include a real vendor or Modelithics model for Capacitors or not but surely its choice for designers to make.

excellent demonstration !! I have question you have added ground plane cond2 in LNA design(both in substrate setting and in layout window). but when I used to define substrate as you did in LNA design video and cond2 layer in layout window as well, I didn't acquire desire results.

@BhargavaAnurag

Жыл бұрын

Hi Rabbia, I am not sure what mistake your might have but just check if you do VIA holes in layout as well as defined the same in your stackup? If doesn't resolve the issue then kindly contact your local Keysight tech support team for assistance.

Thank you so much for the great videos. Can i may ask about placing the vias. can you please tell in which video you described placing of vias! thanks :)

@BhargavaAnurag

3 жыл бұрын

Hi Taha, I am not sure which vias placement you are referring but if you look at videos 41-43 under Learn ADS in 5mins playlist, all your questions should be answered: kzread.info/head/PL9OnCetH8TYrWFGB4QkDP8HVaY-Aum6Hc

Hi Anurag, At 14:43 you made Zs = Zin* to demonstrate the conjugate match's effect on noise figure. However, NFmin is the noise power available from the network, meaning it is only a function of GammaS, while S11(technically GammaIn in this example) is a function of GammaL. That means the return loss would change when output matching circuit was added to network as well, would it not? Then, the comparison is rather qualitative rather than rigorous. Do I understand this correctly? Thanks for the video!

@BhargavaAnurag

3 жыл бұрын

Hi, Yes, you got it right. The concept I showed was for qualitative purposes and by no means it was meant to do rigorous analysis. Main idea was to show how things could be based on the matching criteria you select on the input side assuming output is terminated in a specific impedance. All devices are bilateral in nature and source & load termination conditions will affect the overall performance but this process gives designer some initial boundaries to work with and proceed with the design work. Hope this helps.

Very good explaination. I want to simulate the LNA in Cadence virtuoso. Can you suggest dedicated videos or manual for this? Please reply as soon as possible.

@BhargavaAnurag

Жыл бұрын

You will need to contact Cadence team for getting help

Thank you very much for these wonderful tutorials. Sir, I have a query. When I put the value of intersect point of noise and gain circle in place of 50 Ohm term at input side and S22* at the output term, I got my desired results according to my requirement. I also designed the matching networks individually for input and output matching circuits giving very accurate S11 and S21 at the design frequency. But the problem is when I insert these lumped components design network into the schematic, the results are not similar as it should be. Please help me in this regard. Thanks

@BhargavaAnurag

3 жыл бұрын

Hi Faizan, If you are doing impedance matching network design properly then it should work however make sure you turn the port impedances back to 50Ohm when you insert matching network in the overall design else response will be poor.

Great video sir. please tell me which technology have you worked on

@BhargavaAnurag

3 жыл бұрын

I couldn't understand your query? What do you mean by technology?

Thank you very much! I just have a question. What should we do if we need Noise circle to do the impedance match for lower frequency design? Thanks

@BhargavaAnurag

Жыл бұрын

Hi, I am not sure if I am able to understand the query. You should be able to plot Noise Circles as long as you have the non-linear model or a S2P file for the transistor device that contains noise parameters around the desired frequency.

Hello sir, First I wanted to say that I really liked the video. There is a small point that I did not understand after we found that the point( at 12:47) 9.358+j7.508 is the point that we will have to coordinate with as you explained at 12:47 How do I configure the Smith chart Utlilty to perform the matching? (In the previous video we match the input impedance to 50 ohms) Could you explain to me again after we understood what the intersection points of the GAIN and MIN NOISE are, what do I do to match?

Great work sir, thank you so much, however there is something I am missing and that is why did you place your input matching network right after the source impedance knowing that the Bias network is already design to exhibit 50 ohms impedance, shouldn't the input matching network be connected between one 50 ohms terminal of the bias network and the impedance seen looking in the transistor gate ? the same with the output matching network shouldn't it be connected right after the transistor and one port of the bias network which is already designed to exhibit 50 ohms ? please help me !

@BhargavaAnurag

2 жыл бұрын

As a general rule and good design practice the bias network should be the first thing on either side of the active device and then the impedance matching network design should be done.

Hi. Thank you very much for the videos. Being a begineer in the field, I find them incredibly useful. Can you please help me understand what load impedance you specified for the Smith Match 1 and the source impedance you specified for Smith Match 2? Because the load impedance for Smith Match 1 is not the input the impedance of the FET but this has to be taken at the input end of the bias network. Similar case would be for the Smith Match 2. Sorry if I am missing something basic here.

@BhargavaAnurag

Жыл бұрын

Hi, Its purely your choice, as a design practice I never consider FET/transistor's input impedance as as load for my Input Matching network design and I always include Bias network to be a integral part of the device that needs to be matched and I did the same thing here.

@npurushothaman

Жыл бұрын

Thank you very much for your reply. Even after 2 years of uploading the video, you still answer queries patiently. Immense respect to you!! I understand from your explanation that it's best to include the bias network. I guess then, for match 1, the source impedance becomes 50 ohm, and the load is 8-j8 from the S11 smith chart plot. Similar case with the output impedance matching. Thank you once again for the clarification and the wonderful tutorials.

many thanks , but i have one question ,how to do you choose or convert value of ideal mircostrip with 25 ohm which has line width of 2.9 mm in line calc ,but you use another value 0.871889mm

Sir! can you put a full explanation video about how to make a broadband RF power amplifier for wireless applications, including load/source pull simulation to obtain optimum source and load impedance?

@BhargavaAnurag

3 жыл бұрын

PA design topic coming soon...hopefully I will start from mid-November.

@user-nt4nm4fb3u

3 жыл бұрын

@@BhargavaAnurag that's good, thank you sir! Because we are really in the need.

can you explain how you got your source and load starting points on the smith chart for impedance matching please?

@BhargavaAnurag

3 жыл бұрын

Hi Drake, Kindly watch Video9 which part 1 of this video.

Thank you so much sir. I have a question. At 30.48, which view did you select before run the simulation? EmModel or layout?

@BhargavaAnurag

Жыл бұрын

layout view is not for circuit simulation, it should be emmodel so that you can get em simulation results in circuit simulation.

Hi, First I would thank you for these information that you have provided, Second, I want to ask: that I am using version 2020 of ADS, and there is no EM in schematic window (like in the 51:00 minute of this video) thank you very much

@BhargavaAnurag

2 жыл бұрын

Kindly watch this video first to understand the basics and how to get the menu in schematic window: kzread.info/dash/bejne/oKKau7uRkcrensY.html

Hi Anurag! Very nice tutorial on using ADS for LNA Design. I have followed the video till placing input matching layout component on shematic. There, on running simulator, i get following error message: The instance `I__0' has 13 pins, but the view `LNA_lib:Input_Layout2:schematic' has 0 pins. Could you please advise on resolving this issue? Thanks.

@BhargavaAnurag

2 жыл бұрын

Hi, Please click on "Choose View for Simulation" icon and select emmodel or whatever name you gave to the layout model during EM simulation from the list. When you simulate after selecting proper model, it will work fine.

Thank you very much for your efforts While I am trying to simulate the same design there was an error message indicating that (Wlargest/Wsmallest) for MTEE is greater than the 5 and the resistor is shorted. How I can fix this problem ؟

@BhargavaAnurag

3 жыл бұрын

Schematic discontinuity models use analytical equation in Schematic which has their limits to maintain the accuracy of the formulation or the assumption they are build upon and usually for models such as TEE and STEP etc it is 1:5 or 1:10 ratio that they recommend, if you cross that then you will see these kind of warnings in the simulation status. You can ignore them and your simulation will surely run but it is telling you that if there is any reflection happening at that junction it will not be accurately captured in your circuit simulation and when you perform EM simulation you will see increased discrepancy between schematic and EM results. EM simulator are physics based so they don't have any limitations for the width ratio at junctions and will capture any distortion caused due to high width mismatch. Personally, I never like to have this kind of situation as it is not a good design practice (however no one is stopping you in having these in your designs) and if I see this situation after optimization then I will try to create a stepped impedance section for that transition e.g. you can go from 0.2mm width to 0.8mm and then eventually to 3mm instead of directly connecting 0.2mm wide line to 3mm line as then the impedance mismatch will be too high and bigger reflections will surely happen depending on dielectric material and frequency of operation. Hope this helps in some manner?

@ana_anas86

3 жыл бұрын

@@BhargavaAnurag Can I get your email ?

Hello Sir, Suppose I have the S-Parameter Model and do not have the non linear model of device, do i still need to design the biasing network for the device or just design the input or output matching network?

@BhargavaAnurag

5 ай бұрын

you will need to design bias network even if you use S2P file for device otherwise how will you bias the device in real world...😊

Can you make one video tutorial for GPS Low Noise Amplifier? It is very popular in the industry apply right now. Again, Thank you very much.

@BhargavaAnurag

2 жыл бұрын

I am not sure if there is anything special for GPS LNA apart from the fact that it will be different frequency than what is shown in the video. Rest of the concept will remain same, also at GPS frequency you may want to use Discrete Components for matching etc instead of making it all transmission license based design.

Hi, can you please make videos on multistage RF power amplifiers.

@BhargavaAnurag

4 жыл бұрын

Hi Shweta, Will try to do that in future tutorials...

Thank you so much dear I have to get some knowledge about how to design LNA However,i need your helping how to the design of 12-18 GHz ultra-wide bandwidth LNA on GaAs technology Please say something if the frequency increase difficult to optimizing the noisefigure so how to solve this problem?

@BhargavaAnurag

3 жыл бұрын

Hi, I can't help with that specific question as it will largely depend on the technology you are using but take care of the fundamentals will take you there. Make sure you keep the loss in the IP matching network and any other components on the input side to minimum and always use NFmin as your reference point.

hi , thank you so much .. i have some wrong in first design this sentance appear when i run simulation .......Warning detected by hpeesofsim during circuit set up.Unable to resolve variable(s) or functions(s) in expression ` NsCircle1=ns_circle({1.1,1.2,1.3},NFmin,Sopt,Rn/50,51)'NFminRnSopt †

@BhargavaAnurag

3 жыл бұрын

Hi, Your expression seems fine but check following: 1. Have you clicked on Calculate Noise under the Noise tab in the S-Parameter controller? 2. If you are using S2P file for the device then make sure you S2P file contains Noise data along with the usual S-Parameters. Hope this helps

@rorarora3147

3 жыл бұрын

@@BhargavaAnurag thank you very much the problem has solved

Year channel is very good and informative to me.......Is it possible to get a copy of this project?

@BhargavaAnurag

Жыл бұрын

Yes, you can download the example from Keysight Knowledge Center (account & login required): edadocs.software.keysight.com/display/eesofkcads/RF+LNA+Design+with+ADS+-+Step+by+Step+Example

After doing the simulations with the TL models min 23:34 and after with the EM models min 31:56 and finally with the final layout min 35:24; all simulations came out with the same results? I think I followed all steps, did I miss something in the process? Thank you

@BhargavaAnurag

2 жыл бұрын

Hi Javi, This is difficult to support on KZread. I would recommend you to contact your local Keysight tech support for help.

I wish you all the best , really really your videos are useful thanks a million🤗🙏⚘ Just one question, i hope you answer me soon please i need For designing input and out put matching , choosing the best impedances for input and also for output based on noise and gain circular are independant of DC bais network( which dc bais network includes transmission lines) is it correct?? Thank you in advance

@BhargavaAnurag

3 жыл бұрын

Hi Nazli, It depends on how transparent is your DC Bias design to your operating frequency. If you have done a good bias network design then it will present near perfect open circuit at your RF Frequency so you can say that it doesn't have any impact on your matching circuit design and if you haven't done a good job with the same then it will load your circuit affecting the input and output impedances to be matched. However, as a matter of practice I always advice to perform your impedance check or matching WITH DC Bias Network included. Hope this helps.

@nazlizargarpour1854

3 жыл бұрын

@@BhargavaAnurag Hi Dear Anurag, thanks alot for your quick answer. Before designing the DC bias network just by having DC block and DC feed i measure the input and also output matching and also i did them by consedring dc bias network , but the results are different. So it means my designing for dc bias network is not correct!! and after that based on your advice i have to consider imput and output matching with DC bais network. Also i want to research about differntial or push push amplifier and see which one is better for LNA. I would be greatful, if you could please guide me? I just find your youtube channel, i dont know you have further other channels which i can contact you for getting more information ? Again thanks alot dear Anurag

@BhargavaAnurag

3 жыл бұрын

@@nazlizargarpour1854 Sorry but I don't have much experience with Push-Pull so won't be able to help much.

@nazlizargarpour1854

2 жыл бұрын

@@BhargavaAnurag thank you for your reply. no i want to design differential type NOt push push any more.

Hello, sir first I would like to say these videos are very informative and have been very helpful and I have learned a lot from them. But I have a query I am trying to use ATF-36163 and can't seem to figure out the source-drain and gate terminals so can you help me with that also if u had to recommend any other MOSFET for the LNA which would that be. Thank you

@BhargavaAnurag

2 жыл бұрын

It would be easy if you contact your local Keysight tech support team for help. Usually these terminals are well defined for a library component and if you are importing a netlist then Pins show the proper name for G,D,S etc for easier identification.

Sir, did you choose this topology randomly? What is this topology called?

Thank you a lot for your great videos. I have questions regarding the logical values ( the maximum and the minimum values) for the lumped components such as capacitors, inductors, and resistors in the RF industry, which are very important in the optimization process, especially when we want to minimize or maximize the value of a lumped component to reach our goal with minimum error. In addition to that. I found that we could have a high gain (S21) even if the S11 and S22 have bad values ( 0 to -5 dB) and some simulated values greater than zero (+ve). So what does it mean sir, is the value of S21 basically depends on the amplifier and could improved by a low S11 and S22? And apologize for the lengthiness .. with my best regards sir.

@BhargavaAnurag

2 жыл бұрын

Your questions are related to very fundamentals of RF Circuit Design: 1. When using L & C components for your purpose you should check their SRFs and don't use any component where SRF is lower than your desired frequency. 2. S21 has no real meaning or usefulness if you don't have proper S11 and S22 because the power will be reflected resulting in useless circuit.

@abdullahali-lc8mv

2 жыл бұрын

@@BhargavaAnurag thank you so much for your reply and I will follow your advice for sure .. it seems that we are away behind your knowledge sir :) regards

While desining LNA using HEMT for 28 GHz will the steps followed be same or some changes are to be made?

@BhargavaAnurag

Жыл бұрын

The theory will be same but the implementation would be in IC format typical GaAs based MMIC so you will need to adapt it as MMIC format & components

Hello Mr. Bhargava I did the EM-COSIMULATION of my ckt by taking vias as lumped element as you mentioned in the video. Then I did the EM-COSIMULATION by taking Vias as 3-D element. The performance of the ckt degrade and values of lumped elements of ckt changed for optimum performance. I have two shunt cap to gnd through vias(1-via for each cap of size 30 mil dia) And 2-vias to gnd short ckt stub. Which simulation should I take as more accurate.? I will appreciate your help.

@BhargavaAnurag

3 жыл бұрын

Its difficult to comment without seeing your design on the amount of different you are seeing. Lumped model of the VIA should only be used when you hundreds of VIAs that is typically the case with VIAs used for ground plane stitching. For any normal VIAs you shouldn't use lumped models. If this is still a problem then contact your local Keysight support team for help.

@gursewakghuman2790

3 жыл бұрын

@@BhargavaAnurag Thank you Mr Bhargava one more Quick question I have only 6 vias in my design and I am grounding them using copper wire should I include them in EM Simulations or should I just Simulate without taking vias into account or should I take it as wire vias in EM simulation.? your suggestion will be great help.

I would highly appreciate if anyone could link the video for what function explanation. It would mean a lot.

@BhargavaAnurag

2 жыл бұрын

I am not sure if you need a lengthy video about what(), below is what is available in the ADS documentation and its a very simple function which returns the details about the variable/measurement passed to it: x=[10,20,30,40] y=what(x) returns: y Dependency : [ ] Num. Points : [4] Matrix Size : scalar Type : Integer ----------------------------------- y=what(x, 1) returns: y Dependency : [ ] Num. Points : [4] Matrix Size : scalar Type : Integer Block Name: __tmp_XX ----------------------------------- Notes/Equations This function is used to determine the dimensions of a piece of data, the attached independents, the type, and (in the case of a matrix) the number of rows and columns. Use what() by entering a listing column and using the trace expression what(x).

Hi Anurag, this is an amazing tutorial, thank you. may i have your help please ? my results in the schematic with physical Tlines are good but after i made my layout and run cosimulation i get very bad results, not even close to the schematic results. any idea what could possibly went wrong ?

@BhargavaAnurag

10 күн бұрын

Hi, Its not possible to comment without seeing the setup and the results you are getting. Recommend you contact your local Keysight tech support by writing to support@keysight.com

Anurag sir, I have designed a Broadband LNA that covers frequency band (1-5 GHz) and now I want to perform non-linear simulation of it. But I am not getting how can I find OP1dB point OIP3 point of my broadband LNA because in your video you did for a single design frequency i.e., 2.4GHz. Please guide me how I can do the same for my broad-bandwidth (1-5 GHz).

@BhargavaAnurag

3 жыл бұрын

Hi Adnan, In your case OPId and OIP3 will not be single value as it is frequency dependent parameter. You can do frequency sweep and you will get multidimensional data and you can get the P1dB etc at every frequency you simulate. Usually 2 corner frequencies and 1 center freq is sufficient but it is upto you.

@adnannadeem6223

3 жыл бұрын

@@BhargavaAnurag Thank you sir.

At the time 10.32, the point which is read from the gamma circle is 0.3-j0.1. Is it target gamma? and then we are finding target z. right. So 50*(0.3-j0.1) is target gamma. Is my understanding correct?

@BhargavaAnurag

3 жыл бұрын

Hi Tham, 0.3-j*0.1 is the target normalized impedance which you multiply by 50 to unnormalize it to 50Ohms. Target gamma equation is shown on the data display page which will be (targetZ-50)/(targetZ+50) and this is needed to plot point on Smith Chart as we can't plot the impedance on Smith Chart directly. Its always reflection coefficient/Gamma at least in ADS. Hope this clarifies.

Thanks a lot sir, In the output matching, at the minute 18:23 The capacitor was after the Impedance of the circuit, not befor the 50 Ohms At the minute 23:00 the capacitor was before the 50 Ohms I am little confused, when you have used Smith chart you designed circuit to match the 49+j*24 to 50 And you have used it in an opposite way (from 50 to 49+j24), Please, can you explain it, Best regards,

@BhargavaAnurag

2 жыл бұрын

Hi Muhammed, No need to confuse yourself...😊 Its all about what Zs and Zl you used while using Smith Chart tool. In my case I usually prefer to use Zs=50Ohm even if I am designing Output stage matching network. Now if you see its the reverse of the actual case as for output stage Zs should be the output impedance of the amplifiers and Zl should be 50Ohm but because I reversed this definition while designing my network, I need to flip it when I place it on schematic so that I can have Zs and Zl on the correct side. If it is confusing for you then you can simply use Zs & Zl as applicable for your impedances and while doing so you need to use complex conjugate impedance as the notation of Zs is Zs* in the Smith Chart utility. Hope this is clear to you?

@muhammedarramadan9383

2 жыл бұрын

@@BhargavaAnurag thanks, it is clear now 🌷🌷🙏

Hello sir.. thank you so much for the informative lectures. I have two questions that is First: in the impedance matching in Schmitt chart utility the Z=50 ohm but on the ADS circuit layout they are of 25ohm, how is that happening? Second, after designing the input and output layout and designing with the transistor that is in step 7 i am not getting reliable result. Please kindly help me. Thank you.

@BhargavaAnurag

2 жыл бұрын

When you do initial matching network design, 50Ohm reference impedance is kept as default but while optimizing the circuit you can chose to optimize the impedance as well and that is what I have done here. Playing with impedance under your fabrication limits helps in coming up with shorter length transmission lines reducing the over circuit size. It will be difficult for me to comment on your results as I can't see what you have done. I would recommend you to contact your local Keysight tech support team for help.

H Sir, in your EM simulation, I cant see the ground connected to holes? or how the ground plane is defined for EM simulation? I often used syntax "gnd!" to define the bottom layer as a ground layer, so is it true or not? Thank you very much?

@BhargavaAnurag

2 жыл бұрын

Hi, It depends on your stackup definition, if you have Cover plate defined then you don't need to do anything special as that will be used for return path. Incase of conductor layer mapped you can gnd! net name to denote the purpose but you will still need to define the respective layer under Port Editor as I explained in one of the EM simulation videos. In the video you referred there were VIA holes but perhaps you can't see it due to top conductor layer....😊

@annguyendang8388

2 жыл бұрын

@@BhargavaAnurag Thank you very much ^^

@annguyendang8388

2 жыл бұрын

Hi Sir, I have one more question. I am trying to EM simulate my circuit and follow your videos, but it is realized the EM results are so bad, compared to circuit-based results. Is it normal or is there something wrong in my simulation setup. And EM and circuit results must be similar ? Now i am in stuck with this. Thank you!

you are using Msub in your schematic and in your layout the substrate model has 2 metals. (one is used for ground plane). How does these two match ? in your circuit you did not connect your plane to ground (in 36:00 looks like your ground is floating) could you please explain these details ? Thank you.

@BhargavaAnurag

3 жыл бұрын

Hi, MSub already has 2nd layer defined as lossless ground and in EM you have option of keeping a Cover at the stackup bottom and that replicates the MSub condition for EM analysis or you can model it as a finite ground conductor accounting for lossy conductor closer to real PCB. This may or may not make a substantial difference in your results but it is good to model it this way. There is nothing floating at 36:00 like you mentioned, not sure why do you feel ground is floating? All EM component ports are referring to cond2 as a ground and I used TermG (internally grounded) termination. Hope this clarifies....

@eee2058

3 жыл бұрын

@@BhargavaAnurag So when you make port you change the negative from gnd to cond2 ?

@eee2058

3 жыл бұрын

I could not define ports as you said. how you refer ports to cond2 as ground ?

Hi Sir, I saw the S(2,2) was changed after matching S(1,1). So Should we match S(2,2) before or after matching S(1,1)???

@BhargavaAnurag

2 жыл бұрын

Hi, I would recommend to match output side first and then input. Even when you do so, things will be slightly disbalanced so you can run final optimization to fine tune the values for optimum results.

In step 9, when I simulate the final result, I have some shift in S11 and S22, How can I optimeze the TL over the symbol EMModel?

@BhargavaAnurag

Жыл бұрын

You can do so by having a parametric EM model and I would recommend you to contact local Keysight tech support team for help

Hello Mr Bhargava, Increase in Mesh per wave length and increase in numbers of points in EM simulations increase the accuracy of the simulation.? What is optimum mesh per wave length should be used.? What is the optimum number of points per simulation should be used.? Can you please help me with this. I will Appreciate it .

@BhargavaAnurag

3 жыл бұрын

Yes, method of moments usually is a blind solver and it will simply simulate your structure based on the mesh criteria you have provided in the setup and cells/wavelength is one of them. If you have provided less number then your results may not to be accurate but it doesn't matter above a specific number as E-fields won't change any more. Most often looking at the mesh can give you an initial idea about suitability of the mesh density for your design but if you want to have more confidence to make sure you have the optimum and correct mesh for your structure then you can do something like below: 1. Run initial simulation with say 20 cells/wl 2. Increase mesh density to 30 and compare the results, if different in results is negligible then you know your results with 20 cells was fine else discard the earlier results. Increase the density to something like 40 or 50 and repeat the same exercise. 3. Beyond a certain cells/wl, you will virtually see no major difference in the results as fields in your structure won't change any faster and you will have the required density to capture the field variance. While doing above, you need to take care of the RAM and simulation time as it is never a linear relationship and if you make your mesh very complicated then RAM & Sim time can increase exponentially. There is no single cells/wavelength number which can be said to be optimum and it changes from design to design so you will need to perform this kind of mesh convergence analysis yourself when using method of moments solver. For typical RF PCB/Boards 20 cells/wl is a decent number which works most of the time hence the default number used in the emSetup but you can experiment on your own for your specific designs. For FEM, this kind of mesh convergence step is automatically done for every simulation as the first step is to perform is Mesh refinement based on the deltaS number in your setup which is the acceptable matrix variance for your simulation. Hope this helps in some manner.

@gursewakghuman2790

3 жыл бұрын

@@BhargavaAnurag I really appreciate your help and quick response Mr. Bhargava. Your tutorials are very informative and they been keep helping me in my ckt design.

in em simulation, what difference would it made if the type of the pin where SMD and not TML?

@BhargavaAnurag

4 жыл бұрын

Hi Luck, I couldn't understand your question completely. It would help if you could provide more info on what you are asking so that I can answer in more detail. From what I could understand, here is my initial comment; You have different type of Pins that you could in ADS EM simulation like Point Port, Edge Port, Area Pins etc. If this is what you want then it will be good idea to create another short video on this as it is very important for designers to do more accurate EM analysis.

@ltteogoali7251

4 жыл бұрын

@@BhargavaAnurag please do that, but in addition i asked that after creating a pin, you can chose its type as TML SMD DELTA gap,.. so could you explain this as well

@BhargavaAnurag

4 жыл бұрын

@@ltteogoali7251 Sure, now I am clear. What you want to ask is detail about Port Calibration....

Another question, sir, at 26:07, how to process the lumped elements, such as capacitor and resistor, in the layout generation?

@BhargavaAnurag

3 жыл бұрын

Kindly watch this video: kzread.info/dash/bejne/nnd5sMeghN2eZMo.html and also this for better awareness: kzread.info/dash/bejne/Y5-NlbB_k8eeoJc.html

@hejoshua4170

3 жыл бұрын

@@BhargavaAnurag Thx for your quick reply, sir.

Thank you Anurag. Please I have gotten to the Co-simulation part but receiving this error: ERROR: (stdcmds.ael line 135, column 12) Error generating netlist for "MyLNAs_lib:Part2_Step9:schematic": Failed to create netlist: There is no corresponding terminal for `P3 connected by position 3' in the netlisted view `MyLNAs_lib:Part2_Step8_OPMatch_EM:schematic'. How do I sort this out?

@BhargavaAnurag

Жыл бұрын

I guess you forgot to select the emmodel from Choose View for Simulation.

@EduardoNavarroSabariegos

Жыл бұрын

@@BhargavaAnurag I have same error, but I´ve choosen EMmodel for creating the simbol, any other possible solution?

@EduardoNavarroSabariegos

Жыл бұрын

@@BhargavaAnurag Any special way to define the ports in the layout or in the EM simulation ?

@EduardoNavarroSabariegos

Жыл бұрын

Solve!

Sir I'm working on mmic lna at 94GHz and the required gain I'm getting at 80GHz. Sir how can I tune the output at the desired frequency.

@BhargavaAnurag

3 жыл бұрын

Hi Nishant, Its difficult to comment on this without seeing the design and it will largely depend on the topology and how you designed the circuit. You can try to contact Keysight tech support team to look at your circuit and offer their suggestions.

@nishantposwal356

3 жыл бұрын

@@BhargavaAnurag thankyou so much sir i got the desired result by applying the various combination of the values of the lumped capacitor and inductor i am using at this frequency. Sir if i may ask whats the top cell in gds file?i am facing few problems in eDRC of the layout. thanks in advance

Sir, a problem is that, after the symbol at 52:44 is generated, when I go back to the layout view, all my MLINs and MTEEs were converted to the "ads_device" layer, have you ever met this problem? thank you.

@BhargavaAnurag

2 жыл бұрын

I am not sure how are you going back to the layout view so hard to comment. I would recommend to contact your local Keysight tech support team for help as that will be easier to troubleshoot the issue.

@hezehua5194

2 жыл бұрын

@@BhargavaAnurag ok, I will contact the support team. Make it simple, after the look-alike symbol of the layout is used in the schematic, the MLINs in the layout will be on ads_device layers(blue color MLIN), and the cond() layer will not accept any MLIN or MTEEs, very tricky.

@BhargavaAnurag

2 жыл бұрын

@@hezehua5194 Your explanation is confusing, The layout symbol doesn't do anything to the original layout and you can do whatever you want but to reflect the changes, you need to delete the symbol and recreate the same again as it doesn't change dynamically.

@hezehua5194

2 жыл бұрын

will recreate the symbol, it's hard to describe the problem without pictures,lol, I don't know the application scenario of the ads_device layer, and why the all the components on the cond() layer turn into ads_device layer automatically.

Sir how can we Increase the bandwidth, I am trying to build a broadband low noise amplifier, Is there a way we can connect with you LinkedIn maybe? In desperate need of some guidance . Thanks in advance!

@BhargavaAnurag

3 жыл бұрын

Hi Shaurya, Broadband has different meaning for different people. What the center frequency and bandwidth you are looking at?

@adv_x8848

3 жыл бұрын

@@BhargavaAnurag Hi, Thanks for the reply, by broadband i meant something around 1-10 Ghz

@BhargavaAnurag

3 жыл бұрын

@@adv_x8848 If you want to design LNA for the 1GHz-10GHz band then it's not possible at the PCB level. You will need to design it using MMIC technology which you cannot fabricate easily as you will need to sign up a suitable foundry like UMS, WIN Semi, etc. If you don't want to fabricate but still want to design a broadband LNA using the MMIC process then you can try using MMIC DemoKit that's available in ADS.

can this be done in COMSOL Multiphysics?

@BhargavaAnurag

2 ай бұрын

I don't think so

Hello Sir.. is it possible you can share the project? Thank you

@BhargavaAnurag

Жыл бұрын

Hi, Would you be able to download it from Keysight Knowledge Center?

18:19 why there is so many element in matching circuit. We can do with just two of movement.

@BhargavaAnurag

6 ай бұрын

Lesser matching components can also do your job, but your matching will be narrowband and very sensitive to components or PCB etching tolerances. Having few more components gives you broadband performance and less sensitive circuits. There is always a compromise between overall circuit/layout size vs. less sensitive circuit design. Hope this helps.

My Co-Simulation Results need a bit of tuning. How do I tune the Layout look-alike circuit?

@BhargavaAnurag

Жыл бұрын

If you want to tune discrete components then process is similar to how you would do for any circuit and if you want to tune the layout part of it then refer to my parametric EM videos.

@mfonuko7420

Жыл бұрын

@@BhargavaAnurag Thank you for this.

how can i download library to get ATF and other components ?

@BhargavaAnurag

3 жыл бұрын

Hi, You don't need to download libraries for ATF etc, its all available under ADS installation folder. Kindly watch this video to understand how to add them to your workspace: kzread.info/dash/bejne/iJpqxriEfNvLZLA.html

@khanhang3685

3 жыл бұрын

thank sir

I cannot find the video on 'what function'. Can someone help me find it?

@BhargavaAnurag

2 жыл бұрын

Hi Afzaal, You don't need a video just for what(). Depending on for what parameter you want information, plot it in a Table/List and change the header to what(parameter name) e.g. plot S21 in a table then modify the S21 header as what(S21) and you will see all the details right there... Hope this helps.

Sir, We create symbol from layout but at times conection we are not able to connect properly due to differences between curser and pin which already there.how can we connect pins

@BhargavaAnurag

3 жыл бұрын

Pls contact local Keysight tech support team to get help.

Hello guys, I was doing well but suddenly I got this error: ERROR: (vapi_aj_runtime.ael line 15897, column 9 in de_copy_cell) Error copying cell "smithdg:SmithChartMatch": Cell "SmithChartMatch" not found. I'm not able now to use smith chart smart tool even when I start a new empty workspace. I searched online for a solution but never found. YOUR HELP IS APPRECIATED :)

@BhargavaAnurag

2 ай бұрын

Hi, It seems you have created fault in some config files. Close ADS and look under your home directory to find hpeesof folder or search for it if you are not sure where is your home directory. Rename hpeesof to something like hpeesof_old and restart ADS which will create new hpeesof automatically and try using Smith Chart tool again. Hope this helps….

@mohammedmansour685

2 ай бұрын

@@BhargavaAnurag Thank you Anurag, yes it happened suddenly, I solved it by switching to another ADS version.

sir, how to insert capacitors in the layout?

@BhargavaAnurag

2 жыл бұрын

You cannot insert electrical components in Layout but only their footprints. You can simply draw 2 rectangles for the desired dimensions as required for your capacitors or any other SMT components

@hejoshua4170

2 жыл бұрын

@@BhargavaAnurag ok, I understand what you mean, btw, I see two “port” -like arrows are added on both side of the MGAP, are those the way you represent the lumped capacitors in the layout?

@BhargavaAnurag

2 жыл бұрын

Kindly watch EM Circuit Cosimulation video under "Learn ADS in 5mins" playlist to get complete idea on how to perform EM/Circuit cosimulation. For every discrete component such as Capacitor, Inductor etc, you place relevant ports in Layout for EM simulation and then bring it over to Schematic for assembly of Layout component alongwith electrical components to see the integrated response.

@hejoshua4170

2 жыл бұрын

@@BhargavaAnurag thx a lot, sir

@hejoshua4170

2 жыл бұрын

@@BhargavaAnurag sir, the capacitor problem has been solved, would you kindly recommend some power/low noise amplifier design books? thanks a lot!

can you share your designed ads file with us?

@BhargavaAnurag

4 жыл бұрын

No cheating please...😊 Try to follow steps on your side with the instructions provided and let me know how it goes for you and then we will see if sharing workspace is really necessary....👍

Sorry, i don't know why my dB(S21)[M10_freq_index] is always on the y-axis.

@BhargavaAnurag

Жыл бұрын

Look at the dependencies properly, maybe you are leaving out another dimension in the array and it could be of format say: dB(S21)[M10_freq_index,::]

@BhargavaAnurag

Жыл бұрын

Look at the video of multi-dimensional data processing under Learn ADS in 5mins playlist

@MR-qi7fc

Жыл бұрын

@@BhargavaAnurag Thanks.

Hai sir this is Deepak, I have got an error while simulating step7 impedance matching circuit, the error message I got ADS-syntax parser error in `', line 131: How can I contact you, sir can you give me your mail ID

@BhargavaAnurag

3 жыл бұрын

Hi Deepak, It seems there is some typo error in the component parameter values or the variable values. Kindly contact local tech support team for help.

@deepakn6244

3 жыл бұрын

@@BhargavaAnurag Yes Sir, I rectified those errors. I am getting a gain of 15. 041dB and noise figure around 1.235dB, stability is around 1.372, and return loss S11= -25.391, S22=-7.195 . Sir, please help me to increase the gain up to 15.8dB and to manage reflection coefficient values less than -15 dB. Please do the needful sir.