Thank you Prof. Patrick. Your lectures were very helpful.
@hastingsmsiska73726 ай бұрын
🎉
@eriowu62548 ай бұрын
This lecture really helps! Thank you professor🥰
@HakunaMatata07079 ай бұрын
How can we determine branching effort bi without knowing the actual size of the logical gates as they are dependent on the capacitances of the gates driven by the driver gate?
@polbatallelargo11819 ай бұрын
at the start, why you say that in the pmos net we've 2C? I understand that in the N net you need that 3C because of R/3 and you have 3 so you obtain R. But shouldn't you have to put 1C , because the worst scenario is R in the pmos net?
@rickliles24609 ай бұрын
Algebra porn
@GuyNChai10 ай бұрын
Very helpful, thanks for sharing 🙏🙏
@walterhernandez176810 ай бұрын
You may or may not be checking your comments anymore, but I just want to say thank you for making your lecture material available online! I received my masters degree in Material Science at UCSD, and I am now working as product marketing in precursor business for semiconductor. I often find myself talking to OEMs and device makers, with little to no knowledge in ICs. Your lectures are super helpful to have meaningful conversation with my customers!
@SJayanth11 ай бұрын
30:30 I think it should be Jc1 = m*Jc2, since current is same & Q2 is m times larger, it's current/area must be m times smaller. I know the numbers were just mistakenly reversed.
@deson4958 Жыл бұрын
Why I didn't find this before the interview....
@ashansandanayake3529 Жыл бұрын
this lecture series is highly beneficial but please dont increase your voice all of a sdden inbetween the lecture! that is very annoying
@mumbaiverve2307 Жыл бұрын
Very well explained Sir. Thank you ! I am curious about one aspect in @43.13 ; wont the three electrodes form a kind of potential divider in the electrolyte? Hence wont the physical distance between the three electrodes affect the current flowing into the counter electrode ?
@kelvintichana5169 Жыл бұрын
This lecture series is just perfect
@HakunaMatata0707 Жыл бұрын
When we say we want to have equal rise and fall delay do we mean equal in worst case or in every possible case?
@rockpadstudios Жыл бұрын
I love this stuff, I wish I could have worked in the semiconductor industry.
@georgematthew1 Жыл бұрын
You still can?
@qemmm118 ай бұрын
You can 😊
@snehamathivanan7679 Жыл бұрын
Great content .... Thank you 🙂
@emreparlak2729 Жыл бұрын
great helper
@anasshaydar4138 Жыл бұрын
you saved my life with this tutorial , i had a school project and i had a huge problem which is how can i get a heart beat signal to use it in python later . I coumdn't find any useful info in the net . When i found this vid , everything got fixed ... thank you
@heyitsmea8883 Жыл бұрын
Why we have to take size 3 for nmos. Why not other number... please anyone answer...
@rishavkumar711 Жыл бұрын
your teaching style is awesome sir....
@umeshdhiman2914 Жыл бұрын
Sir where is lecture 1
@rishavkumar9288 Жыл бұрын
Hii sir ...
@rishavkumar9288 Жыл бұрын
Please provide ppt .. beacuse it can enhance the efficiency..
@w62810616 Жыл бұрын
Thank you, for the circuits in the 29min clock, why NMOS M1 and M2 needed?
@adamedfreadue67212 жыл бұрын
how to determine if it is dynamice or not
@pc...4302 жыл бұрын
Are there any resources available for download (pdf of script/presentation)?
@big_23612 жыл бұрын
i think you will be my saviour this semester. thanks very much
@nigeriantoday88422 жыл бұрын
You're not just a lecturer but a teacher and a good one. spending 40mins watching and critically noting down points is worth it and by far more than the 72 hours i spent on the chapter in class.. thank you so much.
@tringo89232 ай бұрын
for real???
@matteofeike65232 жыл бұрын
so difficult to me.. need to read the textbook
@haongothaianh64312 жыл бұрын
Thank you for your lecture sir.
@dungquach80682 жыл бұрын
can you give me the link of reference?
@rushinde92 жыл бұрын
Thanks for sharing this, professor. Any way to get a downloadable copy of these notes?
@onelivingsoul29622 жыл бұрын
Sir can you explain Kogge stone and Brent Kung adders in more detail? As well as Dadda Multiplier & Barrel Shifters
@matthewrampersad81852 жыл бұрын
Great video. Wish you taught in my college
@emreyilmaz20682 жыл бұрын
Amazing video
@matteofeike65232 жыл бұрын
Excuse Professor, do you have some related books recommend?
@arshahtsham1116 Жыл бұрын
"CMOS VLSI Design: A Circuits and Systems Perspective" by Neil H.E. Weste and David Harris is a highly recommended book for VLSI CMOS design. It covers the basics of digital integrated circuit design using the CMOS technology and provides a comprehensive overview of the principles and techniques of modern VLSI design. The book covers a broad range of topics, from basic transistor operation and logic gates to complex digital systems and manufacturing issues. The book also includes numerous examples, exercises, and case studies to reinforce the concepts discussed. It is widely used as a textbook in undergraduate and graduate courses on VLSI design and has been praised for its clarity, depth, and practicality.
@skylerpretto12212 жыл бұрын
Whew! These lectures are saving my ass right now.
@alexandrospanag2 жыл бұрын
At 9:10 you said that the worst case scenario would be to calculate 1 one transistor turns on (the other 2 are switched off ) but in pull-down network you calculated all of them switched ON. This is a mistake therefore making the rest solution false.
@alexandrospanag2 жыл бұрын
CMOS VLSI 4th edition by Neil H. E. Weste & David M. Harris can also prove that what you solved is wrong
@WonderingSoccer2 жыл бұрын
If you ever had a chance to get interviewed by Apple related IC design position, you would be regret for not coming here earlier, thanks for the lecture, prof!!!
@WonderingSoccer2 жыл бұрын
Prof, please allow me to add some memo here to explain why there is 2 on PUN and 3 on PDN: To equal PUN and PDN drive strength, assume the both network resistance: PUN-R = PDN-R = R, and we know for each transistor in PUN, it is generalized with 2R/K and for PDN, it is R/K So, for PUN-R: 1* (2R/K) = R, K = 2 For PDN-R: 3* (R/K) = R, K= 3 That is why PUN has 2C on both drain and source of each transistor and PDN has 3C on each…
@heyitsmea8883 Жыл бұрын
@@WonderingSoccer sir what happens if we take k = 4 for nmos. Because it so confusing. Please answer
@bradleymorgan82232 жыл бұрын
Very well-presented video! I'm trying to build my own lab bench supply, and i think the Brokaw Cell might be just what i needed!
@ytubeleo2 жыл бұрын
At 40:00, I can't see any advantage in CMRR at all, compared to using the same gain of 80 dB (10,000) with the single op amp difference amplifier design mentioned earlier. The improved CMRR just comes from using a gain of 10,000 instead of 100. It appears to be nothing to do with using a fully-differential-mode amplifier before the difference amplifier. The only benefit seems to be high input impedance (which is definitely a great feature) but that could be achieved with buffer amps. In fact, the three op amp design reduces the allowable Vcm common-mode voltage compared to the single op amp design (otherwise the output of the input amps will saturate due to gain in the first stage). The only advantage I can find is the ability to set/adjust the gain with a single resistor. Or am I missing something here? Thanks!
@chaowang7722 жыл бұрын
I agree with you about the CMRR part. But I think the reason why we usually not use a gain of 10,000 instead of 100 may be that such a larger feedback resistor is hard to implement on chip and the matching will get worse too.
@ytubeleo2 жыл бұрын
@@chaowang772 I take your point about large resistors, but, for example, a gain of 10,000 can be achieved with 100k and 10k. I've seen amplifier and other chips with >100k resistors - far easier than 10M for example. Also, my understanding that matching resistors is easier on chip - for example by laser trimming - and they remain at a more balanced temperature, etc. Why would the matching get worse (given that we care about relative errors not absolute errors)?
@willis936Ай бұрын
It's because 1% is a high tolerance for this application. You would typically use matched resistor networks with relative tolerance below 0.025%, which bumps CMRR a few orders of magnitude.
@aryankr2 жыл бұрын
Thank you very much for explaining this in a great detail.
@amruthn32722 жыл бұрын
Couldn't understand the partial derivative part at 34:00
@manideepp22292 жыл бұрын
@@skylerpretto1221 he used curled d bcoz 'p' is another variable although F is constant, we only want to differentiate w.r.t N only keeping p as constant.
@ytubeleo2 жыл бұрын
At 02:45, this comment is basically back-to-front. American doctors almost always say EKG whereas I believe almost all of Europe says ECG apart from when speaking in German (and the probably most of the rest of the world). Certainly in the UK it's only ever called ECG.
@ChrisCoulston2 жыл бұрын
I am teaching microelectronics for the first time this semester. I've been rewriting the labs, seeking to make them more engaging. Early on I identified ECG measurement as something that would have broad appeal. Needless to say I've had limited success getting my basic circuit to work. Thanks for sharing this lecture series; it will help me take a lot of the guess work out of my design process. Your lecture is well organized has quality content and thoughtfully presented; your students are lucky to have you.
@youneslaababid94312 жыл бұрын
how to do the AC analyse for the IA
@AllenSA_Lily3 ай бұрын
Yes
@4BohrKid2 жыл бұрын
Great video
@jasonjung29642 жыл бұрын
Thank you, It's been a great help.
@LaplacianFourier2 жыл бұрын
How is it that everyone is showing the same 3 input NAND example Elmore Delay? Has no one in the history of the internet and text book figured out how to do do the Elmore Delay for a 3 input NOR gate? Sad reflection of educators for the EE field.
Пікірлер
Lecture 1 not uploaded?
Fantastic presentation. Thanks for sharing.
Thank you Prof. Patrick. Your lectures were very helpful.
🎉
This lecture really helps! Thank you professor🥰
How can we determine branching effort bi without knowing the actual size of the logical gates as they are dependent on the capacitances of the gates driven by the driver gate?
at the start, why you say that in the pmos net we've 2C? I understand that in the N net you need that 3C because of R/3 and you have 3 so you obtain R. But shouldn't you have to put 1C , because the worst scenario is R in the pmos net?
Algebra porn
Very helpful, thanks for sharing 🙏🙏
You may or may not be checking your comments anymore, but I just want to say thank you for making your lecture material available online! I received my masters degree in Material Science at UCSD, and I am now working as product marketing in precursor business for semiconductor. I often find myself talking to OEMs and device makers, with little to no knowledge in ICs. Your lectures are super helpful to have meaningful conversation with my customers!
30:30 I think it should be Jc1 = m*Jc2, since current is same & Q2 is m times larger, it's current/area must be m times smaller. I know the numbers were just mistakenly reversed.
Why I didn't find this before the interview....
this lecture series is highly beneficial but please dont increase your voice all of a sdden inbetween the lecture! that is very annoying
Very well explained Sir. Thank you ! I am curious about one aspect in @43.13 ; wont the three electrodes form a kind of potential divider in the electrolyte? Hence wont the physical distance between the three electrodes affect the current flowing into the counter electrode ?
This lecture series is just perfect
When we say we want to have equal rise and fall delay do we mean equal in worst case or in every possible case?
I love this stuff, I wish I could have worked in the semiconductor industry.
You still can?
You can 😊
Great content .... Thank you 🙂
great helper
you saved my life with this tutorial , i had a school project and i had a huge problem which is how can i get a heart beat signal to use it in python later . I coumdn't find any useful info in the net . When i found this vid , everything got fixed ... thank you
Why we have to take size 3 for nmos. Why not other number... please anyone answer...
your teaching style is awesome sir....
Sir where is lecture 1
Hii sir ...
Please provide ppt .. beacuse it can enhance the efficiency..
Thank you, for the circuits in the 29min clock, why NMOS M1 and M2 needed?
how to determine if it is dynamice or not
Are there any resources available for download (pdf of script/presentation)?
i think you will be my saviour this semester. thanks very much
You're not just a lecturer but a teacher and a good one. spending 40mins watching and critically noting down points is worth it and by far more than the 72 hours i spent on the chapter in class.. thank you so much.
for real???
so difficult to me.. need to read the textbook
Thank you for your lecture sir.
can you give me the link of reference?
Thanks for sharing this, professor. Any way to get a downloadable copy of these notes?
Sir can you explain Kogge stone and Brent Kung adders in more detail? As well as Dadda Multiplier & Barrel Shifters
Great video. Wish you taught in my college
Amazing video
Excuse Professor, do you have some related books recommend?
"CMOS VLSI Design: A Circuits and Systems Perspective" by Neil H.E. Weste and David Harris is a highly recommended book for VLSI CMOS design. It covers the basics of digital integrated circuit design using the CMOS technology and provides a comprehensive overview of the principles and techniques of modern VLSI design. The book covers a broad range of topics, from basic transistor operation and logic gates to complex digital systems and manufacturing issues. The book also includes numerous examples, exercises, and case studies to reinforce the concepts discussed. It is widely used as a textbook in undergraduate and graduate courses on VLSI design and has been praised for its clarity, depth, and practicality.
Whew! These lectures are saving my ass right now.
At 9:10 you said that the worst case scenario would be to calculate 1 one transistor turns on (the other 2 are switched off ) but in pull-down network you calculated all of them switched ON. This is a mistake therefore making the rest solution false.
CMOS VLSI 4th edition by Neil H. E. Weste & David M. Harris can also prove that what you solved is wrong
If you ever had a chance to get interviewed by Apple related IC design position, you would be regret for not coming here earlier, thanks for the lecture, prof!!!
Prof, please allow me to add some memo here to explain why there is 2 on PUN and 3 on PDN: To equal PUN and PDN drive strength, assume the both network resistance: PUN-R = PDN-R = R, and we know for each transistor in PUN, it is generalized with 2R/K and for PDN, it is R/K So, for PUN-R: 1* (2R/K) = R, K = 2 For PDN-R: 3* (R/K) = R, K= 3 That is why PUN has 2C on both drain and source of each transistor and PDN has 3C on each…
@@WonderingSoccer sir what happens if we take k = 4 for nmos. Because it so confusing. Please answer
Very well-presented video! I'm trying to build my own lab bench supply, and i think the Brokaw Cell might be just what i needed!
At 40:00, I can't see any advantage in CMRR at all, compared to using the same gain of 80 dB (10,000) with the single op amp difference amplifier design mentioned earlier. The improved CMRR just comes from using a gain of 10,000 instead of 100. It appears to be nothing to do with using a fully-differential-mode amplifier before the difference amplifier. The only benefit seems to be high input impedance (which is definitely a great feature) but that could be achieved with buffer amps. In fact, the three op amp design reduces the allowable Vcm common-mode voltage compared to the single op amp design (otherwise the output of the input amps will saturate due to gain in the first stage). The only advantage I can find is the ability to set/adjust the gain with a single resistor. Or am I missing something here? Thanks!
I agree with you about the CMRR part. But I think the reason why we usually not use a gain of 10,000 instead of 100 may be that such a larger feedback resistor is hard to implement on chip and the matching will get worse too.
@@chaowang772 I take your point about large resistors, but, for example, a gain of 10,000 can be achieved with 100k and 10k. I've seen amplifier and other chips with >100k resistors - far easier than 10M for example. Also, my understanding that matching resistors is easier on chip - for example by laser trimming - and they remain at a more balanced temperature, etc. Why would the matching get worse (given that we care about relative errors not absolute errors)?
It's because 1% is a high tolerance for this application. You would typically use matched resistor networks with relative tolerance below 0.025%, which bumps CMRR a few orders of magnitude.
Thank you very much for explaining this in a great detail.
Couldn't understand the partial derivative part at 34:00
@@skylerpretto1221 he used curled d bcoz 'p' is another variable although F is constant, we only want to differentiate w.r.t N only keeping p as constant.
At 02:45, this comment is basically back-to-front. American doctors almost always say EKG whereas I believe almost all of Europe says ECG apart from when speaking in German (and the probably most of the rest of the world). Certainly in the UK it's only ever called ECG.
I am teaching microelectronics for the first time this semester. I've been rewriting the labs, seeking to make them more engaging. Early on I identified ECG measurement as something that would have broad appeal. Needless to say I've had limited success getting my basic circuit to work. Thanks for sharing this lecture series; it will help me take a lot of the guess work out of my design process. Your lecture is well organized has quality content and thoughtfully presented; your students are lucky to have you.
how to do the AC analyse for the IA
Yes
Great video
Thank you, It's been a great help.
How is it that everyone is showing the same 3 input NAND example Elmore Delay? Has no one in the history of the internet and text book figured out how to do do the Elmore Delay for a 3 input NOR gate? Sad reflection of educators for the EE field.
3 input NOR gate is not practically used