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Private intitute irukka
Many are there... But be aware of the fake and fraud institutions.... Before spending money, go directly to the institute and check. Talk with the students studying there. Don't waste your money 👍
Mam still waiting for assertion and functional coverage konjo sikro potingana romba useful ha irukum😊
Coverage and assertion ku munnadi 2 video podanum, athukku oru flow la poitu irukku. Antha 2 videos preparation pannitu iruken. Athukku aprm start pannituven.
@@vlsiforyou ohhh okay mam nandrii , worth to wait😊
Pls post uvm videos also mam
Sure! Will be post once functional coverage and assertion completed
Mam program run pannurathuku compiler pathi solluga. Please mam.
Eda playground use pannunga
Eagerly waiting for assertion and functional coverage video mam, please koncham sikramave upload pannunga 😊
Sure!!! As many people request. Next athu than plan panni iruken.
System verilog assertion video please
Sure!!! Next athu than plan panni iruken.
@@vlsiforyou nandri mam ☺️
Mam, Ethavathu Certification Course Teach Panringala ?
Certification course lam pannala. Ping me in insta, if you have any doubts
Instead of using unique can we use rand c also to generate unique value so that if we r using rand c means we wont get repeated values
MAM , BACKEND VLSI PLEASE TELL ABOUT IT AND TUTORIALS TOO.
Mostly I worked in front end only
@@vlsiforyou mam which is best frontend or backend in basis of package?
@RAHULVECE both are best in terms in package.
Thank you for your constituency uploading videos about sv mam nandriiii..... Mam please system verilog assertion and functional coverage video please
Sure! Will be covered
As a subscriber noticed an issue in this video, and pinged us in Instagram. we have Updated Reuploaded it. kzread.info/dash/bejne/jG2F17Ggk5a9gM4.html Please use this video for better understanding. Thank you!!!
Mam,i am a mechanical engineer 2022 passed out,no experience,naan epdi pcb design and vlsi design department la varuvathu maam?
Neenga learn pannalam, but some companies will expect ece or eee or e&i stream
Mam na vlsi and ece department pathi unga kita pesanum. Intha year na clg join pananum.ece choose panalamnu irukan. So konjam doubt iruku.
Ping me in instagram
Weekly 2 to 5 videos podunga mam.. Nala iruku unga video.. Super mam🔥... But ninga monthly once podringa.. Konjam neraya podunga mam
Will try to upload every week.
@@vlsiforyou ok mam🔥thank u mam.. Every week 2 to 3 videos nathu upload panunga.. Enga college la placement la ethumee solli thara matranga.. Itha pathuthsn place aagunum🙏🙏🙏🙏
Mam inum video podunga mam🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏🙏i will see ur video
2^16 😂 is not 256 right. 2 ^8 is only 256🎉❤
mam now in 2024 it is important to learn vhdl or verilog
70% verilog 30% vhdl
@@vlsiforyou Thanks a lot mam
❤🎉
❤🎉
❤🎉
❤🎉
😂😂😂😂 .*🎉❤
😂❤🎉
Great explanation. Please post UVM videos, it would be very helpful mam
Sure! Thanks for you support
module carry_look_ahead_4bit_tb; reg [3:0] a,b; reg cin; wire [3:0] sum; wire cout; carry_look_ahead_4bit dut(.a(a), .b(b),.cin(cin),.sum(sum),.cout(cout)); initial begin $dumpfile("dump.vcd"); $dumpvars(1); a=0; b=0; cin=0; #10 a=4; b=2; cin=0; #10 a=7; b=5; cin=0; #10 a=3; b=5; cin=1; #20 $finish; end initial $monitor( "A=%d, B=%d, cin= %d, sum=%d, cout=%d,A=%b, B=%b, cin= %b, sum=%b, cout=%b", a,b,cin,sum,cout,a,b,cin,sum,cout); endmodule this is the testbench I have a doubt that can I assume any values for a,b,cin
can i write like this is this correct
Any value you can give to a, b, c inputs
Ok mam
Mam na epa than b.e electrical engineering la vlsi eduthurkan enaku syllabus enna nu theriyala aprm enna la engineering exam lam attend panna mudiyuma pls rly mam
Syllabus pathi enakku therila, unga regulation ku search panna kidaikkum mostly. Illana unga professor kitta kelunga
Please upload how to write a Test bench in system verilog
Ok, will do it
🙏
Very useful Mam....🤝🏻
Thanks for your support
Akka pls continuous ah video upload pannuga. Romba helpfull ah iruku. UVM concept quick ah podunga❤😊
Kandippa, concept ready panni, prepare panni video poda time edukuthu. Sure ah uvm cover pannituven
please upload more constraint interview questions like this mam ,your work is so much great. now i able to understand the constraint mam thank you so much
Thanks for your support! Most of the constrain interview questions are covered. We have uploaded constrains videos ( from SV21). In those videos, we covered constraint interview questions also. Please take a look 👍
Please upload functional coverage
Sure, will be covered after interface
Dollar display and dollar monitor ku difference sollunga sister Tamil la....simulation result la ena changes nadakum nu sollunga
Refer #14 display tasks in verilog, I have explained detailedly
Mam..pls.give some guidance about available open source software for vlsi project.
For experience, you can use EDA Playground.
8:58 Two methods I have mam, please review it 1. val[i] = fact ((( i + 1 ) * 2 ) - 1 ) 2. val[i] = fact ( i + ( i + 1 ) )
Yes, both are correct.
Hi Mam. If we do right shift will it generate only the One's? constraint c1 { data == 1 >> shift ; }
No, we will get 0 for right shift
Ohh Okay.
Please we need a regular videos ,atleast 4 videos in a week mam and pls post videos in Interprocess Communication SystemVerilog Program Block SystemVerilog Clocking
Thanks for your support. I'll try to do it. It's taking more time to prepare, workout, record, edit and upload the video. I am trying to give my best of knowledge. I hope you all understand us.
I'm grateful for your work mam,ur the one and only source to learn SV and Verilog In tamil with Great understanding mam.Thank you so much mam .Keep doing it mam .
wonderfull teaching mam ♥ Thank you for the SV playlist.
Thanks for your support
%2d %2s defines?
d and s are print formats d means decimal and s means string 2 is for space after equal to Example - $display("a =%2d",a); Assume a = 1, Result : a = (space)(space)1
Mam oru standard course pannanu with job offer,ethachu trusted website sollunga
Really I don't know about the online courses. But you can find reputated institute for learning and job offer.
mam pls ensure audio quality. use any audio filter application like dolby on or any similar app. better you must use mic with noise cancellation feature. Apart from all hats off to your effort to make a tech video in tamil. All the very best for your long tech journey.
Thanks for your support. Yes, we implemented our audio quality for further videos. We are using microphone
Please cover all the topics on system verilog and uvm...
Yeah, will cover soon Please subscribe us and share with your friends And follow us on Instagram for any queries
Super sis👏👏Thanks for making videos on system verilog.Do more videos sis!!!!!
Thank you, I will
Upload next video mam🙌
Will upload soon
Pls try to upload 2-3 videos weekly akka it will be helpful for us!
Super akka 👍 please continue...
Sure
really good.can you please exaplain axi or ahb protocol?
Sure, will be done in upcoming videos
@@vlsiforyou thanks
UVM videos post pannunga mam plsss ..
UVM videos post pannunga mam plsss ..
Will upload soon
Please upload next video mam
Sure I will