;free sample code, copy and paste processor 16F684 include "p16f684.inc" ; Configuration settings __CONFIG _INTRC_OSC_NOCLKOUT & _WDT_OFF & _MCLRE_OFF R1 EQU 0x20 ; outer loop counter R2 EQU 0x21 ; inner loop counter C1 EQU 0X22 ; specify file to experiment with ; Define connections #define SER_IN PORTA, 0 ; RA0 connected to 74HC595 SER_IN #define L_Clock PORTA, 1 ; RA1 connected to 74HC595 L_Clock #define Clock PORTA, 2 ; RA2 connected to 74HC595 Clock ; Main program start org 0x0000 goto Initialize ; Main program Initialize: ; Initialize ports bsf STATUS, RP0 ; Switch to Bank 1 clrf ANSEL ; Set all pins to digital clrf TRISA ; Set all pins of PORTA as output bcf STATUS, RP0 ; Switch to Bank 0 CLRF C1 LOOP BITTESTER BTFSC C1, 0 BSF SER_IN ; PORTA, 0 (RA0) controls the serial input on the shift register CALL DELAY CALL SHIFT_CODE BTFSC C1, 1 BSF SER_IN CALL DELAY CALL SHIFT_CODE BTFSC C1, 2 BSF SER_IN CALL DELAY CALL SHIFT_CODE BTFSC C1, 3 BSF SER_IN CALL DELAY CALL SHIFT_CODE BTFSC C1, 4 BSF SER_IN CALL DELAY CALL SHIFT_CODE BTFSC C1, 5 BSF SER_IN CALL DELAY CALL SHIFT_CODE BTFSC C1, 6 BSF SER_IN CALL DELAY CALL SHIFT_CODE BTFSC C1, 7 BSF SER_IN CALL DELAY CALL SHIFT_CODE BSF L_Clock ; L_CLOCK (PORTA, 1) sets or latches previously-sent 8 bits CALL DELAY BCF L_Clock ; L_CLOCK cleared back to low CALL DELAY RRF C1, F ; rotate right f through carry GOTO LOOP SHIFT_CODE ; shift register subroutine BSF Clock ; Clock pin (PORTA, 2), clocks in whatever serial input (PORTA, 0) is doing CALL DELAY BCF Clock CALL DELAY BCF SER_IN CALL DELAY RETLW 0 DELAY MOVLW 0x80 ; adjusted delay time MOVWF R1 AGAIN MOVLW 0x20 MOVWF R2 HERE NOP NOP DECFSZ R2, F GOTO HERE DECFSZ R1, F GOTO AGAIN RETLW 0 END ; Needed to end the program.