No video

Inverter - 1 - CMOS Inverter Construction

Inverter - 1 - CMOS Inverter Construction

Пікірлер: 19

  • @sayanbaidya9724
    @sayanbaidya97242 ай бұрын

    Anyone struggling to find the VDD/2 concept can refer the Inverter 12 - Nmos Transistor ON resistance and Inverter 13 - Elmore delay lectures

  • @jayparekh9768
    @jayparekh97685 ай бұрын

    The way he explained that NMOS should be used in PDN and PMOS should be used in PUN was commendable.

  • @socialogic9777
    @socialogic97772 жыл бұрын

    When did we come across the concept - discharge from Vdd to Vdd/2 for delay purposes? Also, in which lecture equivalent RC model was discussed?

  • @ParminderKaur-zm4kw

    @ParminderKaur-zm4kw

    2 жыл бұрын

    Yea, sir please always upload all the content.

  • @adeddy8138

    @adeddy8138

    2 жыл бұрын

    Yeah i agree I am totally confused in here ? Partially understanding everything

  • @socialogic9777

    @socialogic9777

    2 жыл бұрын

    @@adeddy8138 kzread.info/dash/bejne/nG2fr8xpidWcj7w.html This is the missing lecture, the first 27 minutes

  • @heyitsmea8883
    @heyitsmea88839 ай бұрын

    When pmos discharging why vgs=-vc(t) didn’t get plz explain

  • @adeddy8138
    @adeddy81382 жыл бұрын

    I am totally confused in here ? Partially understanding everything when the concept of vdd/2 for delay purposes taught and when was equivalent rc model taught i did not came accross something like that plzzz upload the videos if anything is missed

  • @ramankumar-re8xh

    @ramankumar-re8xh

    Жыл бұрын

    have u got this videos or not ?

  • @adeddy8138
    @adeddy81382 жыл бұрын

    I think some transistor capacitance videos are missing i am not understanding the vdd/2 concept ,and equivalent rc model and when did module 3 came from jumping from module1

  • @socialogic9777
    @socialogic97772 жыл бұрын

    Why do we think in terms of NAND-NOR logic in CMOS?

  • @VLSI260

    @VLSI260

    9 ай бұрын

    Because they are good at switching time and power consumptions and their logic efforts are less

  • @ajiths1689
    @ajiths16892 жыл бұрын

    i did not understand the expression for charging ..please someone could you explain...

  • @ajiths1689

    @ajiths1689

    2 жыл бұрын

    understand hopefully

  • @anonymousinfinido2540

    @anonymousinfinido2540

    11 ай бұрын

    ​@@ajiths1689did you understand?

  • @gayatri5397
    @gayatri5397 Жыл бұрын

    Sir why is Vdd negative for PMOS charging?

  • @akashekhar

    @akashekhar

    Жыл бұрын

    Revisit device physics. In pmos, channel is formed when gate voltage is lower than threshold voltage.

  • @VLSI260

    @VLSI260

    9 ай бұрын

    Yes

  • @silverfox7011

    @silverfox7011

    3 күн бұрын

    @@akashekhar and why it is not vgs(t)=vdd-vc(t)