Thank you so much. I did pass the Logic Design course in my university with your help.

This guy is next level

Your Karnaugh maps videos really helped me last semester, this certainly deserved more views. Thank you so much Sir and I pray that the Savior Jesus will bless you

I got nerdsniped and realised I couldn't remember how to solve the ripple adder delay, and went looking for information, this was *excellent*, thank you! One thing to note - the diagrams at the end makes the maths far more clear, it really wasn't 'clicking' for me at all until I saw the P & G outputs on the full adder. As soon as I saw that, though, 🤯 instantly got the idea and why it turns adding into a constant time operation! :D Also, I think the looping backwards to the G/P bus might not be the clearest way to teach this - I wonder if pulling apart the CLA into the G/P stage and Adding stage, then running the bus down the middle, would help make it clearer that there's no longer any ripple, that it just flows with each bit 'slice' operating separately, never waiting for another

Helped a ton during my computer architecture course. You are the man when it comes to logic circuits